The present invention relates to computer network interfacing and switching, and more particularly, to an apparatus and method for interfacing a processor to a network switch in a packet switched network.
Local area networks use a network cable or other media to link stations on the network. Each local area network architecture uses a media access control (MAC) enabling network interfaces at each station to share access to a medium. A multiport network switch and a packet switching network is coupled to stations on the network through its multiple ports. Data sent by one station on a network to one or more other stations on the network are sent through the network switch. The data is provided to the network switch over a shared access medium according to the Ethernet protocol. The network switch, which receives the data at one of its multiple ports, determines the destination of the data frame from the information contained within the data frame. The network switch then transmits the data from the appropriate port to which the destination network station is connected.
It is desirable to provide an interface to allow a central processing unit (CPU) to connect to the network switch and access the internal registers of the network switch. This permits software to program any of the network switch registers through the interface, as provided by the CPU. It also allows the CPU to manage the network through the network switch. For instance, when certain frames are problematic, they may be sent to the CPU to resolve as the manager of the network. Also, the CPU can be in control of a virtual local area network (VLAN) set-up and configuration. When a user wants to join a particular VLAN group, a frame may be sent to the CPU indicating the desire of the user to join that particular VLAN.
As can be seen from the above, it is advantageous to allow a CPU to be interfaced with a network switch to permit the CPU to perform network management functions. Concern arises, however, with the transfer of information (data) between the CPU and the network switch memory. The concern is due to the different respective clocking speeds of the CPU and the network switch. For example, the transfer of information between the network switch and an external memory may be performed at a 100 MHz clock rate. By contrast, the transfer of information between the CPU and the network switch may be limited by a 33 MHz clock regime of the CPU. A transfer of information between the CPU and the external memory through the network switch may therefore present problems in the overflow or underflow of data during the transfer of data between the two regimes. An overflow of data may cause accidental overwriting of data during the transfer. For example, data that is being written from the 100 MHz clock regime of the external memory to the 33 MHz clock regime of the CPU may erroneously overwrite a later transferred portion of data over a previously transferred portion of data within a pipeline since the external memory can fill the pipeline faster than the CPU can empty the pipeline. This concern limits the usefulness of a CPU in a management role of a network switch.
There is a need for an interface between a processor and a network switch that allows a data transfer between two systems running at two different clock speeds without creating an underflow or overflow in the transfer of the data.
These and other needs are met by certain methods of the present inventions which provide an interface for transferring information between a first system operating within a first clock regime and a second system operating within a second clock regime that is different from the first clock regime. The interface comprises a first pipeline section connected to the first system, and a second pipeline section connected to the second system. A first system state machine operates in accordance with the first clock regime to transfer information from the first system and the second pipeline section through the first pipeline section. A second system state machine operates in accordance with the second clock regime to transfer information between the second system and the first pipeline section through the second pipeline section. The first system state machine is configured to halt operation upon reaching at least one state and await fulfillment of a specific status condition of the second system prior to continuing operation. The second system state machine is configured to halt operation upon reaching at least one state and await fulfillment of a specific status condition of the first system prior to continuing operation.
The interlocking nature of the first and second system state machines prevents overflow and underflow during transfers of data between the two systems operating under different clock regimes. Upon reaching a certain state, the state machine of the first system must wait until there is an indication that the second system has reached a specific status condition. The same holds true for the second system state machine. Thus, each system state machine is dependent upon the other system for completing operation. For example, when one of the systems is an external memory and the other is a CPU connected to a network switch, the interlocking of the state machines prevents the overflow of data when the faster clocked memory is transferring data to the slower clocked CPU. Similarly, underflow of data is prevented when the CPU is transferring data to the memory since each state machine must wait for the other system to achieve a certain status condition (such as the full or empty status of a pipeline) before proceeding in its operation. Each state machine can thus be assured that the pipeline connected to the other clock regime is empty or full before initiating a transfer between the pipelines and the different clock regimes.
The earlier stated needs are also met by another embodiment of the present invention which provides a network switch for a packet switched network comprising a processor interface configured for connecting between a processor and a memory. This processor interface includes a first pipeline section that connects the processor interface to a processor. A second pipeline section is connected to the first pipeline section and connects the processor interface to a memory. The first and second pipeline sections are operable at different respective clock speeds to respectively transfer data to and from a processor and to and from a memory. The first state machine controls the filling and emptying of the first pipeline section. A second state machine controls the filling and emptying of the second pipeline section. The first and second state machines are interlocked so that transfers of data between the first and second pipeline sections are initiated only when the receiving one of the first and second pipeline sections is empty.
One of the advantages of the interlocking of the first and second state machines is that the clock speeds of the different clock regimes may be changed without requiring re-synchronization of the different state machines. For example, the processor may be clocked at 33 MHz, 25 MHz, or may even be asynchronous. This is because the interlocking of the state machines prevents the transfer of data until the receiving pipeline section is empty. This condition is independent of the clocking speed that is used within the clocking regime.
Additional advantages and novel features of the invention will be set forth in part in the description which follows and in part will be come apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. Advantages of the present invention may be realized and obtained by means of instrumentalities in combinations particularly pointed out in the appended claims.